This invention relates to contact structures to establish electrical contact with contact targets such as pads, electrode, or leads of electronic circuits or devices, and more particularly, to contact structures to be used such as in a probe card to test semiconductor wafers, packaged semiconductor devices, IC chips, printed circuit boards and the like, with an higher speed, frequency range, density and quality.
In testing high density and high speed electrical devices such as LSI and VLSI circuits, high performance contact structures such as probe contactors must be used. The contact structure of the present invention is not limited to the application of testing, including burn-in testing, of semiconductor wafers and die, but is inclusive of testing and burn-in of packaged semiconductor devices, printed circuit boards and the like. However, for the convenience of explanation, the present invention is described mainly with reference to the semiconductor wafer testing.
In the case where semiconductor devices to be tested are in the form of a semiconductor wafer, a semiconductor test system such as an IC tester is usually accompanied with a substrate handler, 400 such as an automatic wafer prober, to automatically test the semiconductor wafer. Such an example is shown in FIG. 1 in which a semiconductor test system has a test head 600 which is ordinarily in a separate housing and is electrically connected to the main frame of the test system with a bundle of cables. The test head and the substrate handler are mechanically and electrically interacted with one another by means of a manipulator 500 driven by a motor 510 and the semiconductor wafers to be tested are automatically provided to a test position of the test head by the substrate handler.
On the test head, the semiconductor wafer to be tested is provided with test signals generated by the semiconductor test system. The resultant output signals from IC circuits on the semiconductor wafer under test are transmitted to the semiconductor test system wherein they are compared with expected data to determine whether the IC circuits on the semiconductor wafer function correctly.
The test head and the substrate handler are connected with an interface component 140 consisting of a performance board 120 which is a printed circuit board having electric circuit connections unique to a test head""s electrical footprint, coaxial cables, pogo-pins and connectors. The test head 600 includes a large number of printed circuit boards 150 which correspond to the number of test channels or test pins. Each of the printed circuit boards has a connector 160 to receive a corresponding contact terminal 121 of the performance board 620. A xe2x80x9cfrogxe2x80x9d ring 130 is mounted on the performance board 620 to accurately determine the contact position relative to the substrate handler 400. The frog ring 130 has a large number of contact pins 141, such as ZIF connectors or pogo-pins, connected to contact terminals 121, through coaxial cables 124.
FIG. 2 shows, in more detail, a structure of the substrate handler (wafer prober) 400, the test head 600 and the interface component 140 when testing a semiconductor wafer. As shown in FIG. 2, the test head 600 is placed over the substrate handler 400 and mechanically and electrically connected to the substrate handler through the interface component 140. In the substrate handler 400, a semiconductor wafer 300 to be tested is mounted on a chuck 180. A probe card 170 is provided above the semiconductor wafer 300 to be tested. The probe card 170 has a large number of probe contactors or contact structures (such as cantilevers or needles) 190 to contact with circuit terminals or contact targets in the IC circuit of the semiconductor wafer 300 under test.
Electrical terminals or contact receptacles of the probe card 170 are electrically connected to the contact pins 141 provided on the frog ring 130. The contact pins 141 are also connected to the contact terminals 121 of the performance board 620 with coaxial cables 124 where each contact terminal 121 is connected to the printed circuit board 150 of the test head 600. Further, the printed circuit boards 150 are connected to the semiconductor test system through the cable 110 having several hundreds of inner cables.
Under this arrangement, the probe contactors 190 contact the surface of the semiconductor wafer 300 on the chuck 180 to apply test signals to the semiconductor wafer 300 and receive the resultant output signals from the wafer 300. The resultant output signals from the semiconductor wafer 300 under test are compared with the expected data generated by the semiconductor test system to determine whether the semiconductor wafer 300 performs properly.
FIG. 3 is a bottom view of the probe card 170 of FIG. 2. In this example, the probe card 170 has an epoxy ring on which a plurality of probe contactors 190 called needles or cantilevers are mounted. When the chuck 180 mounting the semiconductor wafer 300 moves upward in FIG. 2, the tips of the cantilevers 190 contact the pads or bumps on the wafer 300. The ends of the cantilevers 190 are connected to wires 194 which are further connected to transmission lines (not shown) formed in the probe card 170. The transmission lines are connected to a plurality of electrodes 197 which contact the pogo pins 141 of FIG. 2.
Typically, the probe card 170 is structured by a multi-layer of polyimide substrates having ground planes, power planes, signal transmission lines on many layers. As is well known in the art, each of the signal transmission lines is designed to have a characteristic impedance such as 50 ohms by balancing the distributed parameters, i.e., dielectric constant of the polyimide, inductances, and capacitances of the signal within the probe card 170. Thus, the signal lines are impedance matched lines to achieve a high frequency transmission bandwidth to the wafer 300 providing current during steady state and high current peaks generated by the device""s outputs switching. For removing noise, capacitors 193 and 195 are provided on the probe card between the power and ground planes.
An equivalent circuit of the probe card 170 is shown in FIG. 4 to explain the limitation of bandwidth in the conventional probe card technology. As shown in FIGS. 4A and 4B, the signal transmission line on the probe card 170 extends from the electrode 197, the strip (impedance matched) line 196, the wire 194 and the needle (cantilever) 190. Since the wire 194 and needle 190 are not impedance matched, these portions function as an inductor L in the high frequency band as shown in FIG. 4C. Because of the overall length of the wire 194 and needle 190 is around 20-30mm, the significant frequency limitation is resulted in testing a high frequency performance of a device under test.
Other factors which limit the frequency bandwidth in the probe card 170 reside in the power and ground needles shown in FIGS. 4D and 4E. If the power line can provide large enough currents to the device under test, it will not seriously limit the operational bandwidth in testing the device. However, because the series connected wire 194 and needle 190 for supplying the power (FIG. 4D) as well as the series connected wire 194 and needle 190 for grounding the power and signals (FIG. 4E) are equivalent to inductors, the high speed current flow is seriously restricted.
Moreover, the capacitors 193 and 195 are provided between the power line and the ground line to secure a proper performance of the device under test by filtering out the noise or surge pulses on the power lines. The capacitors 193 have a relatively large value such as 10 xcexcF and can be disconnected from the power lines by switches if necessary. The capacitors 195 have a relatively small capacitance value such as 0.01 xcexcF and fixedly connected close to the DUT. These capacitors serve the function as high frequency decoupling on the power lines.
Accordingly, the most widely used probe contactors as noted above are limited to the frequency bandwidth of approximately 200 MHz which is insufficient to test recent semiconductor devices. It is considered, in the industry, that the frequency bandwidth be of at least that equal to the tester""s capability which is currently on the order of 1GHz or higher, will be necessary in the near future. Further, it is desired in the industry that a probe card is capable of handling a large number of semiconductor devices, especially memories, such as 32 or more, in parallel (parallel test) to increase test throughput.
A relatively new type of probe card having membrane contactors is expected to have a sufficiently high bandwidth because it can incorporate impedance matched transmission lines to the tips of the contactors. However, membrane contactors have a disadvantage in that they are deformed by the temperature change to a degree that the contact performance is no longer available. Another disadvantage of the membrane contactors resides in that only limited number of contactors can be fabricated on the membrane because of the difficulty of providing spring forces to the contactors. One last disadvantage inherent in the technology is the lack of individual compliance in the contactors relative to one another. If the contacting surface presents anomalies in topology from one point to another (which become more pronounced over a larger area), this variability cannot be accounted for on an individual basis from one contactor to another. Therefore, membrane contactors are not suitable for testing a large number of devices in parallel.
In the conventional technology, the probe card and probe contactors such as shown in FIG. 3 are manually made, resulting in inconsistent quality. Such inconsistent quality includes fluctuations of size, frequency bandwidth, contact force and resistance, etc. In the conventional probe contactors, another factor making the contact performance unreliable is that the probe contactors and the semiconductor wafer under test have different temperature expansion ratios. Thus, under the varying temperature, the contact positions therebetween vary which adversely affects the contact force, contact resistance and bandwidth.
Therefore, it is an object of the present invention to provide contact structures to be used in testing a semiconductor wafer, packaged LSI and the like which have a very high operating frequency to meet the test requirements in the next generation semiconductor technology.
It is another object of the present invention to provide contact structures to be used in testing a semiconductor wafer, packaged LSI and the like which are suitable for testing a large number of semiconductor devices in a parallel fashion at the same time.
It is a further object of the present invention to provide contact structures to be used in testing a semiconductor wafer, packaged LSI and the like which are produced through a standard semiconductor production process without involving manual assembly or handling, thereby achieving uniform and consistent quality.
It is a further object of the present invention to provide contact structures to be used in testing a semiconductor wafer, packaged LSI and the like, a large number of which can be produced at the same time with uniform and consistent quality.
It is a further object of the present invention to provide contact structures to be used in testing a semiconductor wafer, packaged LSI and the like which are produced through photolithography processes.
It is a further object of the present invention to provide contact structures to be mounted on a probe card for testing a semiconductor wafer, packaged LSI and the like which are capable of compensating temperature expansion coefficient of a semiconductor wafer under test.
In the present invention, a contact structure for testing a semiconductor wafer, a packaged LSI or a printed circuit board (device under test) is formed through a photolithography technology well established in the semiconductor production process and mounted on a surface of the substrate.
The contact structure of the present invention has a beam like shape formed through a photolithography technology. The contact structure is formed of a silicon base having an inclined support portion created through an anisotropic etching process, an insulation layer formed on the silicon base and projected from the inclined support, and a conductive layer made of conductive material formed on the insulation layer so that a beam portion is created by the insulation layer and the conductive layer, where wherein the beam portion exhibits a spring force in a transversal direction of the beam portion to establish a contact force when the tip of the beam portion pressed against a contact target.
Another aspect of the present invention is contact structure mounting a large number of contact beams formed through the photolithography process. The contact structure includes a plurality of contact beams each of which exhibits a spring force in a transversal direction thereof to establish a contact force when the tip of the contact beam pressed against a contact target, where each of the contact beam is comprised of a silicon base having an inclined support portion created through an anisotropic etching process, an insulation layer for electrically insulating the beam portion from one another, and a conductive layer made of conductive material formed on the insulation layer so that a beam portion is created by the insulation layer and the conductive layer, a contact substrate for mounting the plurality of contact beams wherein the contact substrate have grooves for receiving the silicon base therein in a manner to fix the contact beams in a diagonal direction, and a plurality of contact traces provided on a surface of the contact base and respectively connected to the contact beams to establish signal paths toward an electrical component external to the contact substrate.
A further aspect of the present invention is contact structure mounting a large number of contact beams formed through the photolithography process. The contact structure includes a plurality of contact beams each of which exhibits a spring force in a transversal direction thereof to establish a contact force when the tip of the contact beam pressed against a contact target, where each of the contact beam is comprised of a silicon base having two inclined portions at least one of which is created through an anisotropic etching process, an insulation layer for electrically insulating the beam portion from one another, and a conductive layer made of conductive material formed on the insulation layer so that a beam portion is created by the insulation layer and the conductive layer, a contact substrate for mounting the plurality of contact beams wherein the contact substrate have a planar surface for mounting thereon the silicon bases by means of an adhesive to fix the contact beams in a diagonal direction, and a plurality of contact traces provided on a surface of the contact base and respectively connected to the contact beams to establish signal paths toward an electrical component external to the contact substrate.
A further aspect of the present invention is a process for producing the contact structure. The method of producing the contact structure is comprised of the steps of providing a silicon substrate cut in a (100) crystal plane, applying a first photolithography process on an upper surface of the silicon substrate for forming a boron doped layer on a surface of the silicon substrate, forming a first insulation layer on the boron doped layer, forming a second insulation layer on a bottom surface of the silicon substrate, applying a second photolithography process on the second insulation layer for forming an etch window in the second insulation layer, performing an anisotropic etch through the etch window; and applying a third photolithography process on the first insulation layer for forming a conductive layer, where each of the photolithography processes includes steps of photoresist coating, masking, exposure, and photoresist stripping.
According to the present invention, the contactor has a very high frequency bandwidth to meet the test requirements in the next generation semiconductor technology. Since the probe contactor is formed through a modern miniaturization technology used in the semiconductor production process, a large number of contactors can be aligned in a small space which is suitable for testing a large number of semiconductor devices at the same time.
Since the large number of probe contactors are produced at the same time on the substrate with the use of the microfabrication technology without involving manual handling, it is possible to achieve consistent quality, high reliability and long life in the contact performance. Further, because the probe contactors can be fabricated on the same substrate material as that of the device under test, it is possible to compensate the temperature expansion coefficient of the device under test, which is able to avoid positional errors.